HAL QSPI constants migration

This section provides information about the HAL QSPI constants migration .

Note

All constants are migrated using the following concepts:

HAL QSPI address size

HAL1

HAL2 



#define QSPI_ADDRESS_8_BITS
#define QSPI_ADDRESS_16_BITS
#define QSPI_ADDRESS_24_BITS
#define QSPI_ADDRESS_32_BITS

typedef enum
{
  HAL_XSPI_ADDR_8BIT,
  HAL_XSPI_ADDR_16BIT,
  HAL_XSPI_ADDR_24BIT,
  HAL_XSPI_ADDR_32BIT
} hal_xspi_addr_width_t;

HAL QSPI address mode

HAL1

HAL2 



#define QSPI_ADDRESS_NONE
#define QSPI_ADDRESS_1_LINE
#define QSPI_ADDRESS_2_LINES
#define QSPI_ADDRESS_4_LINES

typedef enum
{
  HAL_XSPI_ADDR_NONE,
  HAL_XSPI_ADDR_1LINE,
  HAL_XSPI_ADDR_2LINES,
  HAL_XSPI_ADDR_4LINES,
  HAL_XSPI_ADDR_8LINES
} hal_xspi_addr_mode_t;

HAL QSPI alternate bytes size

HAL1

HAL2 



#define QSPI_ALTERNATE_BYTES_8_BITS
#define QSPI_ALTERNATE_BYTES_16_BITS
#define QSPI_ALTERNATE_BYTES_24_BITS
#define QSPI_ALTERNATE_BYTES_32_BITS

typedef enum
{
  HAL_XSPI_ALTERNATE_BYTES_8BIT,
  HAL_XSPI_ALTERNATE_BYTES_16BIT,
  HAL_XSPI_ALTERNATE_BYTES_24BIT,
  HAL_XSPI_ALTERNATE_BYTES_32BIT
} hal_xspi_alternate_bytes_width_t;

HAL QSPI alternate bytes line

HAL1

HAL2 



#define QSPI_ALTERNATE_BYTES_NONE
#define QSPI_ALTERNATE_BYTES_1_LINE
#define QSPI_ALTERNATE_BYTES_2_LINES
#define QSPI_ALTERNATE_BYTES_4_LINES

typedef enum
{
  HAL_XSPI_ALTERNATE_BYTES_NONE,
  HAL_XSPI_ALTERNATE_BYTES_1LINE,
  HAL_XSPI_ALTERNATE_BYTES_2LINES,
  HAL_XSPI_ALTERNATE_BYTES_4LINES,
  HAL_XSPI_ALTERNATE_BYTES_8LINES
} hal_xspi_alternate_bytes_mode_t;

HAL QSPI automatic stop

HAL1

HAL2 



#define QSPI_AUTOMATIC_STOP_DISABLE
#define QSPI_AUTOMATIC_STOP_ENABLE

typedef enum
{
  HAL_XSPI_AUTOMATIC_STOP_DISABLED,
  HAL_XSPI_AUTOMATIC_STOP_ENABLED
} hal_xspi_automatic_stop_status_t;

HAL QSPI clock mode

HAL1

HAL2 



#define QSPI_CLOCK_MODE_0
#define QSPI_CLOCK_MODE_3

typedef enum
{
  HAL_XSPI_CLOCK_LOW,
  HAL_XSPI_CLOCK_HIGH
} hal_xspi_clock_polarity_t;

HAL QSPI data mode

HAL1

HAL2 



#define QSPI_DATA_NONE
#define QSPI_DATA_1_LINE
#define QSPI_DATA_2_LINES
#define QSPI_DATA_4_LINES

typedef enum
{
  HAL_XSPI_REGULAR_DATA_NONE,
  HAL_XSPI_REGULAR_DATA_1LINE,
  HAL_XSPI_REGULAR_DATA_2LINES,
  HAL_XSPI_REGULAR_DATA_4LINES,
  HAL_XSPI_REGULAR_DATA_8LINES,
  HAL_XSPI_REGULAR_DATA_16LINES
} hal_xspi_regular_data_mode_t;

HAL QSPI instruction mode

HAL1

HAL2 



#define QSPI_INSTRUCTION_NONE
#define QSPI_INSTRUCTION_1_LINE
#define QSPI_INSTRUCTION_2_LINES
#define QSPI_INSTRUCTION_4_LINES

typedef enum
{
  HAL_XSPI_INSTRUCTION_NONE,
  HAL_XSPI_INSTRUCTION_1LINE,
  HAL_XSPI_INSTRUCTION_2LINES,
  HAL_XSPI_INSTRUCTION_4LINES,
  HAL_XSPI_INSTRUCTION_8LINES
} hal_xspi_instruction_mode_t;

HAL QSPI match mode

HAL1

HAL2 



#define QSPI_MATCH_MODE_AND
#define QSPI_MATCH_MODE_OR

typedef enum
{
  HAL_XSPI_MATCH_MODE_AND,
  HAL_XSPI_MATCH_MODE_OR
} hal_xspi_match_mode_t;

HAL QSPI sample shifting

HAL1

HAL2 



#define QSPI_SAMPLE_SHIFTING_NONE
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE

typedef enum
{
 HAL_XSPI_SAMPLE_SHIFT_NONE,
 HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE
} hal_xspi_sample_shift_t;

HAL QSPI send instruction mode

HAL1

HAL2 



#define QSPI_SIOO_INST_EVERY_CMD
#define QSPI_SIOO_INST_ONLY_FIRST_CMD

typedef enum
{
  HAL_XSPI_SIOO_DISABLED,
  HAL_XSPI_SIOO_ENABLED
} hal_xspi_sioo_status_t;

HAL QSPI timeout activation

HAL1

HAL2 



#define QSPI_TIMEOUT_COUNTER_DISABLE
#define QSPI_TIMEOUT_COUNTER_ENABLE

typedef enum
{
  HAL_XSPI_TIMEOUT_DISABLE,
  HAL_XSPI_TIMEOUT_ENABLE
} hal_xspi_timeout_activation_t;

HAL QSPI DDR mode

HAL1

HAL2 



#define QSPI_DDR_MODE_DISABLE
#define QSPI_DDR_MODE_ENABLE

typedef enum
{
   HAL_XSPI_DATA_DTR_DISABLED,
   HAL_XSPI_DATA_DTR_ENABLED
} hal_xspi_data_dtr_status_t;

HAL QSPI dual flash mode

HAL1

HAL2 



#define QSPI_DUALFLASH_DISABLE
#define QSPI_DUALFLASH_ENABLE

typedef enum
{
  HAL_XSPI_MEMORY_SINGLE,
  HAL_XSPI_MEMORY_DUAL
} hal_xspi_memory_mode_t;

HAL QSPI flash select

HAL1

HAL2 



#define QSPI_FLASH_ID_1
#define QSPI_FLASH_ID_2

typedef enum
{
  HAL_XSPI_IO_7_0,
  HAL_XSPI_IO_7_4,
  ...
} hal_xspi_io_select_t;

HAL QSPI DDR data output delay

HAL1

HAL2 



#define QSPI_DDR_HHC_ANALOG_DELAY
#define QSPI_DDR_HHC_HALF_CLK_DELAY

typedef enum
{
  HAL_XSPI_DELAY_HOLD_NONE,
  HAL_XSPI_DELAY_HOLD_QUARTCYC
} hal_xspi_delay_hold_t;

HAL QSPI flags

HAL1

HAL2 

#define QSPI_FLAG_BUSY
#define QSPI_FLAG_FT
#define QSPI_FLAG_SM
#define QSPI_FLAG_TC
#define QSPI_FLAG_TE
#define QSPI_FLAG_TO

#define HAL_XSPI_FLAG_BUSY
#define HAL_XSPI_FLAG_FT
#define HAL_XSPI_FLAG_SM
#define HAL_XSPI_FLAG_TC
#define HAL_XSPI_FLAG_TE
#define HAL_XSPI_FLAG_TO
#define HAL_XSPI_FLAG_ALL

Related concept:

HAL QSPI interrupts

HAL1

HAL2 

#define QSPI_IT_TO
#define QSPI_IT_SM
#define QSPI_IT_FT
#define QSPI_IT_TC
#define QSPI_IT_TE

#define HAL_XSPI_IT_TO
#define HAL_XSPI_IT_SM
#define HAL_XSPI_IT_FT
#define HAL_XSPI_IT_TC
#define HAL_XSPI_IT_TE
#define HAL_XSPI_IT_ALL

Related concept:

HAL QSPI error code

HAL1

HAL2 

#define HAL_QSPI_ERROR_NONE
#define HAL_QSPI_ERROR_TRANSFER
#define HAL_QSPI_ERROR_TIMEOUT
#define HAL_QSPI_ERROR_DMA
#define HAL_QSPI_ERROR_INVALID_CALLBACK
#define HAL_QSPI_ERROR_INVALID_PARAM

#define HAL_XSPI_ERROR_NONE
#define HAL_XSPI_ERROR_TRANSFER
#define HAL_XSPI_ERROR_TIMEOUT
#define HAL_XSPI_ERROR_DMA

Related concept: Revised and optimized HAL error management

HAL QSPI timeout definition

HAL1

HAL2 

#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE

Relocated to the source file as a private constant, as it is not intended for user access.

HAL QSPI chip select high time

HAL1

HAL2 

#define QSPI_CS_HIGH_TIME_1_CYCLE
#define QSPI_CS_HIGH_TIME_2_CYCLE
#define QSPI_CS_HIGH_TIME_3_CYCLE
#define QSPI_CS_HIGH_TIME_4_CYCLE
#define QSPI_CS_HIGH_TIME_5_CYCLE
#define QSPI_CS_HIGH_TIME_6_CYCLE
#define QSPI_CS_HIGH_TIME_7_CYCLE
#define QSPI_CS_HIGH_TIME_8_CYCLE

These defines have been removed in HAL2 and replaced by the cs_high_time_cycle parameter within the hal_xspi_timing_config_t structure, which accepts values ranging from 1 to 64.